In semiconductor technology, due to its characteristics, gallium nitride (GaN) is used to form various integrated circuit devices, such as high power field-effect transistors, high frequency transistors, or high electron mobility transistors (HEMTs). In one example, a GaN enhancement mode transistor is formed in an integrated circuit. The enhancement mode transistor is normally off when no bias voltage is applied to the corresponding gate. In a conventional GaN enhancement mode transistor, the gate structure is designed to have a p-type doped cap layer formed on an active region (see, for example, U.S. Patent Application Publication No. 2010/0258842). Then, a metal layer is formed on the p-type doped cap layer and is designed for voltage bias. However, this gate structure in the enhancement mode transistor suffers large gate leakage when the transistor is turned on. The large gate leakage will limit the transistor's performance and safe operating range. Therefore, a structure for a GaN enhancement mode transistor with reduced gate leakage to address the above issues and a method of making the same are needed.